Linux kernel hang on pcie3 init

Mixtile Core 3588E
#1

Hello, we have board developed for Nvidia jetson tx2nx, now we are trying to replace tx2nx with core3588e.
After load module pcie-dw-rockchip, linux kernal hang.

If I add to dts:

&pcie30phy {
    status = "disabled";
};
&pcie3x4 {
    status = "disabled";
};

linux kernel NOT hang.

linux kernel downloaded from GitHub - mixtile-rockchip/kernel (branch: mixtile/core3588e/ubuntu/kernel5.10)

dts part about pcie3 (from arch/arm64/boot/dts/rockchip/rk3588-mixtile-core3588e.dts):

&pcie30phy {
    rockchip,pcie30-phymode = <PHY_MODE_PCIE_AGGREGATION>; /* P1:PCIe3x2  +  P0:PCIe3x2 */
    status = "okay";
};

&pcie3x4 {
        reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
        vpcie3v3-supply = <&vcc3v3_pcie30>;
        pinctrl-names = "default";
        pinctrl-0 = <&pcie30x4m1_pins>;
    supports-clkreq;
        status = "okay";
};

maybe I need to change something with clkreq?

On pcie3 we have NVME SSD (sch in attachements).

c
c1522×1500 492 KB

PCIE0_RST# pin 181
PCIE0_CLKREQ# pin 180

#2

Hello Dmitry, when utilizing your carrier board with the Nvidia Jetson TX2 NX, have you noticed any issues with the NVME SSD’s operation? Could you possibly share the model number of your NVME SSD with us? This information will be helpful as we work to pinpoint and resolve the existing issue.

#3

There are no problems with the same disk and carrier board with Nvidia Jetson TX2 NX. We are using SSD ADATA_IM2P33E8-512GP .

#4

Hello Dmitry, thanks for information.
While reviewing the schematic of your carrier board, we came across some apparent irregularities with the PCIe data lanes connections, namely PETn and PETp. It appears they might be inversely connected. For instance, M.2 pin37 PETp1 seems to be connected to PET1_N and similar connections are observed elsewhere. We are reaching out to determine if this was an intentional aspect of your design, or if perhaps we may be misunderstanding the schematic. Your clarification will be immensely helpful.

#5

Our circuit designer says this is done for ease of routing and that the PCIE standard allows for reversal in the line.

#6

Hello Dmitry, we double confirmed with the chip manufacturer and the PCIE controller of RK3588 does not support the exchange of positive and negative pins of the PCIE data differential line. We are very sorry for the inconvenience about this.